Research interests

Nicolas Farrugia obtained a M.Sc in Signal and Image processing in 2005 and a PhD Degree in electronics for image processing in 2008. In October 2010, he joined the Music Performance and Brain Lab as a postdoctoral fellow. He is involved in research projects on movement dynamics in percussion music performance (using motion capture). He is also interested in studying sensorimotor synchronization, as a tool for music-based therapy and rehabilitation in patients with motor disorders.

Publications 

Farrugia, N. , Mamalet, F. , Roux, S. , Yang, F. & Paindavoine, M. (2009). Fast and Robust Face Detection on a Parallel Optimized Architecture implemented on FPGA. IEEE Transactions on Circuits and Systems for Video Technology, 19 (4), pp. 597-602.

Farrugia, N. , Mamalet, F. , Roux, S. , Yang, F. & Paindavoine, M. (2008). Design of a Real-time face detection parallel architecture using High-Level Synthesis. EURASIP Journal on Embedded Systems, Article ID 938256, vol. 2008, 2008. (available online at http://www.hindawi.com/journals/es/2008/938256.html)

Brost, V. , Yang, F. , Paindavoine, M. & Farrugia, N. (2007). Multiple Modular VLIW Processors based on FPGA. Journal of Electronic Imaging, Article ID 24163

Research presentations

Quinson, C., Farrugia, N. & Paindavoine, M. (2008). On the need of semi-automated source to source transformations in the Used Guided High level synthesis tool. "Workshop on HLS at DAC (Design Automation Conference)", Los Angeles, United States, August. .

Farrugia, N. ., Mamalet, F. , Roux, S. , Yang, F. & Paindavoine, M. (2007). A Parallel Face Detection System Implemented On FPGA. "IEEE conference - International Symposium on Circuits and Systems (ISCASS'07)", New Orleans, U.S.A, May.

Farrugia, N. , Mamalet, F. , Roux, S. , Yang, F. , Paindavoine, M. (2007). Implantation Parallèle de la détection de visages : Méthodologie et implantation sur FPGA. "GRETSI", Troyes, France, September.

Farrugia, N. , Mamalet, F. , Roux, S. , Yang, F. , Paindavoine, M. (2007). HLS-based Implementation of Real-time face detection parallel architecture. "Design of Applied Signal and Image Processing (DASIP)", Grenoble, France, November.

Farrugia, N. , Auge, I. , Petrot, F. , Mamalet, F. & Paindavoine, M. (2008). A convolutional neural network hardware architecture designed with the UGH tool. "Workshop on High Level Synthesis (HLS) at Design, Automation and Test in Europe (DATE)", Munich, Germany, March.

Brost, V. , Yang, F. , Paindavoine, M. & Farrugia, N. (2007). A Modular VLIW Processor. "International Symposium on Circuits and Systems (ISCASS'07)", New Orleans, U.S.A, May.